Through silicon via (TSV) has become one of the key emerging trends of three-dimensional (3D) packages, as it can realize vertically interconnect between stacked-dies. Due to large mismatch in thermal expansion coefficients (CTE) between the copper via and the silicon, significant mechanical stresses are induced at the interfaces when TSV structure is subjected to thermal stresses, which would greatly affect the reliability and electrical performance of TSV 3D device. In this paper, the relationship between the state of stresses and failure of TSV had been explored by combining finite element model simulation (FEM) and failure physical analysis. The position of the maximum stress of the TSV structure was obtained by FEM analysis. The relationship of stress and displacement change with temperature was also studied. And a thermal cycling experiment was conducted to validate the simulation results. Physical failure analysis after thermal cycling experiment was